Rezultate preconizate
- 1 carte de cercetare
- 2 lucrari la reviste indexate in baze de date internaționale (ISI, Scopus)
- 4 lucrari la conferinte cu volume indexate in baze de date internaționale (ISI Proceedings)
- 1 cerere de brevet
Rezultate realizate
- Lucrari publicate in reviste indexate ISI:
- B. S. Kirei, V. I. M. Chereja, S. A. Hintea, M. D. Topa, “PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits“, Advances in Electrical and Computer Engineering, vol.19, no.1, pp.9-16, 2019, doi:10.4316/AECE.2019.01002
- Robert Groza, Ioana-Adriana Potarniche, B. S. Kirei, Marina D. Topa, “Digitally controlled oscillator for all-digital frequency locked loops“, Romanian Journal of Information Science and Technology, Volume 21, Number 1, 2018, pg. 3-17, ISSN 1453-8245
- Lucari publicate la conferinte indexate ISI Proceedings:
- Sergiu-Alex Ranga, B. S. Kirei, Marina D. Topa, “An Equivalent Circuit for Flying-Adder Frequency Synthesizer and Its VHDL Implementation“, 60th International Symposium ELMAR-2018, 16-19 September 2018, Zadar, Croatia, doi: 10.23919/ELMAR.2018.8534646
- Verginia-Iulia-Maria Chereja, Adriana-Ioana Potarniche, Sergiu-Alex Ranga, B. S. Kirei, Marina D. Topa, “Power Dissipation Estimation of CMOS Digital Circuits at the Gate Level in VHDL“, 2018 International Symposium on Electronics and Telecommunications (ISETC), Timisoara, 2018, pp. 1-4, doi: 10.1109/ISETC.2018.8583957
- Erwin Szopos, Ioana Saracut, B. S. Kirei, Marina D. Topa, “Discrete Domain Modeling of an All-Digital Frequency Locked Loop“, 40th International Semiconductor Conference CAS-2017, 11-14 October 2017, ISBN: 978-1-5090-3985-2, pg. 247-250, Sinaia, Romania
- Robert Groza, Gabor Csipkes, B. S. Kirei, Marina D. Topa, “Digitally controlled current-mode quadrature oscillator“, 40th International Semiconductor Conference CAS-2017, 11-14 October 2017, ISBN: 978-1-5090-3985-2, pg. 261-264, Sinaia, Romania
- Kirei, Calin Farcas, Robert Groza, Marina D. Topa, “An All-Digital Frequency Locked Loop and Its Linearized s-domain Model“, 59th International Symposium ELMAR-2017, 18-20 September 2017, Zadar, Croatia
- Cerere de Brevet
- Bibliotecă VHDL pentru modelarea ADPLL-urilor la nivel de poartă cu estimarea consumului și a ariei ocupate